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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CLIDR, Cache Level ID Register</h1><p>The CLIDR characteristics are:</p><h2>Purpose</h2>
        <p>Identifies the type of cache, or caches, that are implemented at each level and can be managed using the architected cache maintenance instructions that operate by set/way, up to a maximum of seven levels. Also identifies the Level of Coherence (LoC) and Level of Unification (LoU) for the cache hierarchy.</p>
      <h2>Configuration</h2><p>AArch32 System register CLIDR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-clidr_el1.html">CLIDR_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to CLIDR are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>CLIDR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="2"><a href="#fieldset_0-31_30">ICB</a></td><td class="lr" colspan="3"><a href="#fieldset_0-29_27">LoUU</a></td><td class="lr" colspan="3"><a href="#fieldset_0-26_24">LoC</a></td><td class="lr" colspan="3"><a href="#fieldset_0-23_21">LoUIS</a></td><td class="lr" colspan="3"><a href="#fieldset_0-20_0">Ctype7</a></td><td class="lr" colspan="3"><a href="#fieldset_0-20_0">Ctype6</a></td><td class="lr" colspan="3"><a href="#fieldset_0-20_0">Ctype5</a></td><td class="lr" colspan="3"><a href="#fieldset_0-20_0">Ctype4</a></td><td class="lr" colspan="3"><a href="#fieldset_0-20_0">Ctype3</a></td><td class="lr" colspan="3"><a href="#fieldset_0-20_0">Ctype2</a></td><td class="lr" colspan="3"><a href="#fieldset_0-20_0">Ctype1</a></td></tr></tbody></table><h4 id="fieldset_0-31_30">ICB, bits [31:30]</h4><div class="field">
      <p>Inner cache boundary. This field indicates the boundary for caching Inner Cacheable memory regions.</p>
    <table class="valuetable"><tr><th>ICB</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Not disclosed by this mechanism.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>L1 cache is the highest Inner Cacheable level.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>L2 cache is the highest Inner Cacheable level.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>L3 cache is the highest Inner Cacheable level.</p>
        </td></tr></table></div><h4 id="fieldset_0-29_27">LoUU, bits [29:27]</h4><div class="field"><p>Level of Unification Uniprocessor for the cache hierarchy.</p>
<p>For a description of the values of this field, see <span class="xref">Terminology for Clean, Invalidate, and Clean and Invalidate instructions</span>.</p>
<div class="note"><span class="note-header">Note</span><p>This field does not describe the requirements for instruction cache invalidation. See <a href="AArch32-ctr.html">CTR</a>.DIC.</p></div><div class="note"><span class="note-header">Note</span><p>When <span class="xref">FEAT_S2FWB</span> is implemented, the architecture requires that this field is zero so that no levels of data cache need to be cleaned in order to manage coherency with instruction fetches.</p></div></div><h4 id="fieldset_0-26_24">LoC, bits [26:24]</h4><div class="field"><p>Level of Coherence for the cache hierarchy.</p>
<p>For a description of the values of this field, see <span class="xref">Terminology for Clean, Invalidate, and Clean and Invalidate instructions</span>.</p></div><h4 id="fieldset_0-23_21">LoUIS, bits [23:21]</h4><div class="field"><p>Level of Unification Inner Shareable for the cache hierarchy.</p>
<p>For a description of the values of this field, see <span class="xref">Terminology for Clean, Invalidate, and Clean and Invalidate instructions</span>.</p>
<div class="note"><span class="note-header">Note</span><p>This field does not describe the requirements for instruction cache invalidation. See <a href="AArch32-ctr.html">CTR</a>.DIC.</p></div><div class="note"><span class="note-header">Note</span><p>When <span class="xref">FEAT_S2FWB</span> is implemented, the architecture requires that this field is zero so that no levels of data cache need to be cleaned in order to manage coherency with instruction fetches.</p></div></div><h4 id="fieldset_0-20_0">Ctype&lt;n&gt;, bits [3(n-1)+2:3(n-1)], for n = 7 to 1</h4><div class="field">
      <p>Cache Type fields. Indicate the type of cache that is implemented and can be managed using the architected cache maintenance instructions that operate by set/way at each level, from Level 1 up to a maximum of seven levels of cache hierarchy.</p>
    <table class="valuetable"><tr><th>Ctype&lt;n&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b000</td><td>
          <p>No cache.</p>
        </td></tr><tr><td class="bitfield">0b001</td><td>
          <p>Instruction cache only.</p>
        </td></tr><tr><td class="bitfield">0b010</td><td>
          <p>Data cache only.</p>
        </td></tr><tr><td class="bitfield">0b011</td><td>
          <p>Separate instruction and data caches.</p>
        </td></tr><tr><td class="bitfield">0b100</td><td>
          <p>Unified cache.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>If software reads the Cache Type fields from Ctype1 upwards, once it has seen a value of 000, no caches that can be managed using the architected cache maintenance instructions that operate by set/way exist at further-out levels of the hierarchy. So, for example, if Ctype3 is the first Cache Type field with a value of 000, the values of Ctype4 to Ctype7 must be ignored.</p></div><div class="access_mechanisms"><h2>Accessing CLIDR</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b001</td><td>0b0000</td><td>0b0000</td><td>0b001</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID2 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID4 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TID2 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR2.TID4 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        R[t] = CLIDR;
elsif PSTATE.EL == EL2 then
    R[t] = CLIDR;
elsif PSTATE.EL == EL3 then
    R[t] = CLIDR;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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